1. Field of the Invention
The present invention relates to testing of integrated circuits and more particularly concerns improved membrane probes.
2. Description of Related Art
Integrated circuits or chips including conductive traces, electrical components, and active devices are fabricated in batches of large numbers of similar or identical circuits on a single wafer and then individually cut from the wafer for use. Because production techniques and processes are pushed to the limits of accuracy and repeatability, significant numbers of circuits fabricated on a single wafer may prove to be unacceptable or inoperable. Therefore, before each circuit is separated from the others by severing the wafer into its many component circuits for its intended use, it is desirable to test each circuit individually.
Probe cards presently employed for testing of integrated circuits while still on the wafer employ a number of probe contact elements, commonly in the form of very small blades or needles that are mechanically and electrically fixed to a circuit board or the like and have leads that fan out to outer edges of the probe card for making connections between the probe card and testing circuitry. The contact blades or needles of the probe card are moved into contact with specific areas, namely the pads of the integrated circuit or chip under test, and may be electrically connected so as to apply selected input signals and to read output signals from the device under test. In this manner the chips are tested on the wafer, before being connected for intended use, by applying operating signals and monitoring and evaluating resultant outputs.
In the use of such probe cards, the contact between the probe card blades or needles and the circuit chip is frequently made by a scrubbing action, which tends to deflect the slender probe elements as much as several mils on each touchdown. This displacement, which occurs repetitively upon each test, further tends to change the desired positioning of the elements.
The probe may have from fifty to several hundred contacts, each of which must be precisely and individually positioned with respect to all others so that upon contact with the circuit chip all probe contacts will contact all pads of the chip under test. All of this means that the probe cards presently used are exceedingly expensive, require much maintenance, and are subject to many errors.
As integrated circuit speeds increase, so too do the difficulty and extent of the testing problems. Such problems are caused by cross-talk between adjacent signal traces, signal loss and degradation due to capacitative loading of the circuit under test, and increased need for shielding and impedance matching of signal lines throughout the test fixture and test head. High frequency probe transmission lines must be properly terminated. Although high frequency hardware can be provided up to the test head itself, the physical connection between the test head and the integrated circuit pad, which relies upon exposed metallic blades or needles, provides poor high frequency performance and extremely fragile components. Thus the final part of the probe transmission line cannot be properly terminated.
As size and spacing of integrated circuit chips decrease and density of chip contacts increases, it becomes ever more difficult to make mechanical blade or needle contacts as small and closely spaced as required for proper testing of modern integrated circuit chips. Moreover, the great bulk and complex configuration of prior art probe cards do not readily lend themselves to automated handling or simplified storage.
My U.S. Pat. No. 5,148,103 describing apparatus for testing integrated circuits has a number of features including employing a flexible diaphragm, conductive contact pads and an arrangement for applying pressure to one side of the flexible diaphragm to accomplish self planarizing contact of the probe pads against the pads of a die or chip under test. U.S. Pat. No. 5,148,103 also provides probe arrangements that adapt the probe for use in wafer testing processes using conventional pick and place loading and cassette storage of both membrane probes and test wafers.
However, neither the U.S. Pat. No. 5,148,103 nor any other known arrangement provides for economically fast full-wafer testing at high temperatures nor for a number of improvements that are available with the methods and apparatus described herein. Membranes of the prior art have a single port, which is not suitable for full wafer burn-in testing, i.e., simultaneous testing of all or substantial numbers of the hundreds of chips on a three, six or eight inch diameter wafer, because the deflection, or sag, of a large single membrane is too severe for chips, and even contacts, widely separated on the wafer. Although numerous attempts have been made by others to avoid excessive sag in the testing for individual chips (see, e.g., U.S. Pat. No. 5,264,787 to Woith et al., assigned to the assignee of the present application), no suitable solution to the problem of simultaneous testing of plural chips has been known heretofore.
Additionally, the diaphanous nature of the membrane in a single large aperture probe precludes mounting of the heavier circuit elements such as decoupling capacitors and isolating resistors within that central aperture, at points close to the test contacts.
Accordingly, it is an object of the present invention to provide for multi-chip testing of integrated circuit chips while avoiding or minimizing the problems mentioned above.